(1) Field of the Invention
This invention relates generally to analog-to digital converters and relates more particularly to low-noise and low offset continuous-time Sigma-Delta Modulators. The principle can be used also for many continuous-time modulators, because it replaces the necessity for return-to-zero code (RZ) and hence improves ISI and distortion. The disadvantage of RZ code is degrading of frequency characteristics.
(2) Description of the Prior Art
Oversampling modulation techniques have become popular today for high-resolution analog signal processing applications such as data conversion and signal generation. The major reason for their popularity comes about because their implementations rely less on the matching of analog components and amplifier gains, and more on digital signal processing. This is advantageous today as submicron VLSI technologies are more amenable for integrating complex digital signal processing operations than analog operations.
Sigma-delta converters offer high resolution, high integration, and low cost, making them a good ADC choice for applications such as process control and weighing scales. The Sigma-Delta (ΔΣ) modulation is a kind of analog-to-digital signal conversion derived from the delta modulation.
It is a challenge for the designers of sigma delta modulators to achieve low noise and low offset continuous time delta-sigma modulators wherein inter-symbol-interference (ISI) is kept to a minimum. ISI arises from the fact that the channel performs a linear convolution of its impulse response with the time-domain waveform. This means that independent symbols affect each other; one symbol “bleeds” into another.
A known solution to circumvent this non-linear effect is to implement a return-to-zero scheme, as disclosed in U.S. Pat. No. (6,369,730 to Blanken et al.). A return-to-zero switch switches the output current iDAC of a second voltage-to-current converter to zero for part of a clock period T. This return-to-zero switching in the feedback branch takes place synchronously with the sampling frequency of the sigma-delta modulator. Furthermore Blanken et al. disclose that said output current can be switched to zero in parallel with the input to avoid mismatch in frequency characteristics.
Another solution is described in ISSCC' 02: “A 10 μV-offset 8 kHz Bandwidth 4th order Chopped sigma-Delta A/D converter for Battery management”. A DAC signal switches in a chopping frequency the polarity of a reference voltage at the input of transconductors. Three transconductors are used wherein one of them is always connected to zero-input to realize return to zero principle
There are more known patents dealing with the design of delta-sigma modulators:
U.S. Pat. No. (6,160,506 to Pellon) proposes a sigma-delta analog-to-digital feedback converter arrangement achieving low noise and a wide dynamic range by use of a directional coupler as a summing device for generating the difference signal on which the forward sigma-delta analog-to-digital converter operates. The feedback is provided by a digital-to-analog reconstructor, which applies the reconstructed analog signal to the tap of the directional coupler, in which the feedback signal is summed with the analog input signal. A low-noise amplifier is coupled to the output of the directional coupler at which the difference signal appears, so the dynamic range of the signal traversing the low-noise amplifier is small. The high isolation between the tap of the directional coupler and the source of analog signals allows the use of an input bandpass filter.
U.S. Pat. No. (6,891,488 to McDaniel et al.) discloses an Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.
U.S. Pat. No. (6,907,374 to Tsyrganovich) discloses a self-calibrating sigma-delta converter (SCADC) functioning in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error; gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.